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Wishbone interface implementation
by Unknown on Mar 17, 2004 |
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Is ethernet's wishbone interface considered "Wishbone Classic" or
"Wishbone Registered Feedback"?
Which type of burst accesses are supported? The wishbone spec talks
about "constant address burst cycle", "incrementing burst cycle"
and "End-of-Burst" and "block cycles".
Does the ETH_REGISTERED_OUTPUTS define need to be on in order to
allow bursting to happen?
Thanks so much,
Linda Conrad
----- Original Message -----
From: Igor Mohor(opencores)igorm@o...>
To:
Date: Tue Mar 16 22:18:59 CET 2004
Subject: [ethmac] Can the opencore Ethernet wishbone interface be
directlyconnect ed to an Altera Avalon bus?
Hi.
Ethernet does single accesses and burst accesses (read and write). The worst case is when the buffer descriptor is pointing to the address 0x1 (0x5, 0x9...). In that case first a single byte cycle is started (address is 0x1), then a single half cycle is started (address = 0x2) and then word burst is started (from address 0x4). Since Ethernet has a 32-bit interface, byte cycle means that only one select signal is active. For half cycle 2 select signals are set. Regards, Igor
> -----Original Message-----
> From: ethmac-bounces@o...
[mailto:ethmac-bounces@o...]
> On Behalf Of Conrad, Linda A
> Sent: Tuesday, March 16, 2004 9:52 PM
> To: 'ethmac@o...'
> Subject: [ethmac] Can the opencore Ethernet wishbone interface
be
> directlyconnect ed to an Altera Avalon bus?
> > I would like to know how to connect an Altera Avalon bus directly to the
> ethernet core from opencore.
> I've made a guess, but at this point in time I don't know what are all the
> types of wishbone bus cycles
> that the ethernet core's wishbone interface produces . I need to connect
> the ethernet core's wishbone slave
> interface to an Avalon master, and the ethernet core's wishbone master
> interface to an Avalon slave.
>
> Any help is greatly appreciated,
>
> Linda Conrad
> StorageTek
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/ethmac
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